1 www.pericom.com 01/25/13 pi3hdmi1310 -a hdmi? switch with non-blocking eq circuitry features ? differential channel 3:1 mux/demux for tdms signals ? 3:1 mux/demux for ddc signals ? non-eq blocking circuitry to utilize ideal eq found in main receiver chipset ? low power consumption to support energy star compliance ? data rate support up to 3.4gbps (16bit color depth per channel) ? 2 pin control for port selection ? 3.3v power and 5v standby power ? esd protection on all i/o pins 8kv contact per iec61000-4-2 7kv hbm per jesd22 ? packaging (pb-free & green): 72 - contact tqfn description pericom semico nductors pi3hdmi? series of switch circuits are tar geted for high-resolution video networks that are based on dvi/hdmi standards. the PI3HDMI1310-A is a 3-to-1 hdmi mux/demux switch. it is designed for low bit-to-bit skew and high channel-to -channel noise isolation. the maximum dvi/ hdmi data rate of 3.4gbps provides the resolution required by next generation hdtv and pc graphics. three dif ferential channels are used for data (video signals for dvi or audio/video signals for hdmi), and one dif ferential channel is used for clock for decoding the tmds signals at the outputs. PI3HDMI1310-A was designed specifcally to meet a tc-sink requirement for the hpd ports. the high speed video ports and ddc ports can be either source or sink. all tmds i/o pins are protecte d with pericom's esd protection circuits, supporting protection against esd damage as high as 8 kv contact per iec6000-4-2 spec. block diagram 4 - differential ? d0-d3a tmds lanes d0-d3b d0-d3c 4 - differential ? 4 - differential ? tmds lanes tmds lanes 4 - differential ? tmds lanes d0-d3 ddc_clk ddc_data ddc_clk a ddc_data a ddc_data c ddc_data b ddc_clk b ddc_clk c hpd_a hpd_c hpd_b hpd_sink control logic sel1 sel2 oe 100k pin confguration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 292827 323130 353433 36 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 707172 676869 646566 63 gnd d2-a d2+a d3-a d3+a vdd d1-b d1+b d2-b d2+b vdd d3-b d3+b gnd d0-c d0+c vdd d1-c d1+c d2-c d2+c gnd gnd ddc_dataa ddc_clka gnd ddc_datab ddc_clkb vdd50 gnd gnd gnd d0+ gnd d1- d1+ vdd d2- d2+ gnd d3- d3+ vdd d0- gnd gnd d1+a d1-a d0+a d0-a hpdc gnd d0-b d0+b d3-c d3+c ddc_datac ddc_clkc gnd gnd gnd ddc_clk ddc_data vdd oe sel1 sel2 hpd_sink vdd hpdb hpda vdd50 12-0196
2 www.pericom.com 01/25/13 pin description pin # pin name pin ty pe description 69, 68, 71, 70, 3, 2, 5, 4, dxa (x = 0, 1, 2, 3) i/o port a high speed inputs 8, 7, 10, 9, 12, 11, 15, 14 dxb (x = 0, 1, 2, 3) i/o port b high speed inputs 18, 17, 20, 19, 23, 22, 25, 24 dxc (x = 0, 1, 2, 3) i/o port c high speed inputs 65, 66, 67 hpda, hpdb, hpdc output hpd open-drain outputs for each port. logic will follow truth table on page 7. external 1kohm pull-up to 5v is required 33, 64 vdd50 power 5.0v voltage rail from hdmi/dvi connector. used during standby-mode. 60 hpd_sink input gp i/o pin from scalar. internal 100kohm pull-down. 29, 28, 32, 31, 35, 34, 42, 43 ddc_clkx, ddc_datax i/o i 2 c signals for ddc communication on tmds ports 55, 54, 53, 52, 51, 49, 48, 46, 45 dx (x = 0, 1, 2, 3) i/o 4-diferential high speed output signals 58, 59 sel1, sel2 inputs selection for d0-d3 and ddc signals (select pins, see truth tables on page 5) 6, 13, 21, 44, 50, 56, 61 v dd power 3.3v power supply 1, 16, 26, 27, 30, 36, 37, 38, 39, 40, 41, 53, 62, 63, 72 gnd power ground. 57 oe input output enable (active low). when high, all outputs are hi-z and chip is placed into standby mode. under standby mode, the current supply is from vdd50. PI3HDMI1310-A hdmi? switch with non-blocking eq circuitry 12-0196
3 www.pericom.com 01/25/13 block diagram explanation ddc switch block passive nmos based 3:1 mux for ddc channels from each hdmi/dvi input connector. tis section can remain active even when 3.3v supply is gone, as long as 5.0v from tmds connector is connected to the PI3HDMI1310-A ic. 3:1 high speed diferential channel block 4-diferential channels per port. 3 channels are targeted for high speed data channels (250mbps to 3.4gbps) and 1 channel is targeted for high speed clock signal (25mhz to 340mhz). hpd control channels block drives each hpd channels through the input pin, hpd_sink. tis signal will need to drive external pull-down transistor circuit before connecting to the hdmi/dvi connector. te external pull down circuit will look like the following: hpda hpdb hpdc 5v hpd 5v hpd 5v hpd 1k? 1k? 1k? PI3HDMI1310-A hdmi? switch with non-blocking eq circuitry 12-0196
4 www.pericom.com 01/25/13 truth table for hpdx signals control pins hot plug detect status oe sel1 sel2 hpd_sink hpd a hpd b hpd c x x l l l l l h hi-z l hi-z hi-z hi-z hi-z x x l l h h l h hi-z hi-z hi-z l hi-z hi-z x x h h l l l h hi-z hi-z hi-z hi-z hi-z l x x h h h h l h hi-z hi-z hi-z hi-z hi-z hi-z *all hi-z will become h if external pull-up connected at the output. storage t emperature .................................................... C65c to +150c supply v oltage to ground potential ................................ C0.5v to +4.0v dc input v oltage .............................................................. C0.5v to 4.0v dc output current ....................................................................... 120ma power dissipation ........................................................................... 0.5w note: stresses greater than those listed under maxi - mum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) sel1 sel2 output port 0 0 port a 0 1 port b 1 0 port c 1 1 hi-z truth table for d0-d3 and ddc signals dc electrical characteristics for switching over operating range (t a = C40c to +85c, v dd = 3.3v 10%) parameter description test conditions (1) min ty p (2) max units v ih input high voltage guaranteed high level 1.5 v v il input low voltage guaranteed low level C0.5 0.65 v ik (3) clamp diode voltage v dd = max., i in = C18ma C0.7 C1.2 PI3HDMI1310-A hdmi? switch with non-blocking eq circuitry 12-0196
5 www.pericom.com 01/25/13 dynamic electrical characteristics over the operating range (t a = -40o to +85oc, v dd = 3.3v 10%, gnd=0v) parameter description test conditions min ty p. (2) max units x talk crosstalk on high speed channels see fig. 3 for measure - ment setup f= 1.13 ghz -34 db f = 825 mhz -36 o irr off isolation on high speed channels see fig. 2 for measure - ment setup f= 1.13 ghz -28 f = 825 mhz -32 i loss diferential insertion loss on high speed channels (see fgure 1) dr = 1.54gbps dr = 2.0gbps dr = 2.25gbps dr = 3.0gbps dr = 3.4gbps -1.5 -1.73 -1.82 -1.99 -2.08 db bw -3db bw for tmds channels 3.0 ghz status pins (hpd) - open drain output bufer v ol(ttl) ttl low-level output voltage i ol = 4ma 0.4 v notes: 1. for max. or min. conditions, use appropriate value specifed under electrical characteristics for the applicable device type. 2. typical values are at v dd = 3.3v, t a = 25c ambient and maximum loading. 3. substrate diode voltage drop. for testing reference. power supply characteristics parameters description test conditions (1) min. ty p. (2) max. units i dd operating power supply current v dd = max., v selx = gnd or v dd 6 10 ma i ddq standby supply current oe - high 3 5 i ih input high current v dd = max., v in = v dd 5 a i il input low current v dd = max., v in = gnd 5 i off of leakage current, for high speed channels only vinput = 3.6v, v dd = 0v 50 status pins (hpd_sink) v ih lvttl input high voltage 2 5.3 v v il lvttl input low voltage gnd 0.8 r p pull-down resistance v dd 50 = 5.0v 100k ohm dc electrical characteristics for switching over operating range (t a = C40c to +85c, v dd = 3.3v 10%) parameter description test conditions (1) min ty p (2) max units PI3HDMI1310-A hdmi? switch with non-blocking eq circuitry 12-0196
6 www.pericom.com 01/25/13 test circuit test circuit test circuit fig.1 fig.2 fig.3 PI3HDMI1310-A hdmi? switch with non-blocking eq circuitry 12-0196
7 www.pericom.com 01/25/13 switching characteristics (t a = -40o to +85oc, v dd = 3. 3v10%) parameter description min. max. units t pzh , t pzl line enable time 0.5 25 ns t phz , t plz line disable time 0.5 25 t b-b bit-to-bit skew within the same diferential pair 15 ps t ch-ch channel-to-channel skew 35 r t 4pf c l v dd v in v out 200-ohm 200-ohm 6.0v pulse generator d.u.t test circuit for electrical characteristics (1-5) notes: 1. c l = load capacitance: includes jig and probe capacitance. 2. r t = termination resistance: should be equal to z out of the pulse generator 3. output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50?, t r 2.5ns, t f 2.5ns. 5. te outputs are measured one at a time with one transition per measurement. switch positions test switch t plz , t pzl (output on b-side) 6.0v t phz , t pzh (output on b-side) gnd prop delay open PI3HDMI1310-A hdmi? switch with non-blocking eq circuitry 12-0196
8 www.pericom.com 01/25/13 ordering information ordering code package code package description PI3HDMI1310-Azle zl pb-free and green 72-contact tqfn notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging packaging mechanical: 72-contact tqfn date: 06/10/11 description: 72-contact, very thin quad flat no-lead (tqfn) package code: zl72 document control #: pd-2075 revision: b notes: 1. all dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. 3. refer jedec mo-220 4. recommended land pattern is for reference only. 5. thermal pad soldering area. 6. recommended thermal via diameter (drill size) is 0.3mm and via pitch is 1.27mm. 11-0119 all trademarks are property of their respective owners. note: for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php PI3HDMI1310-A hdmi? switch with non-blocking eq circuitry 12-0196
|
